Accessing SRAM from NIOS and Verilog Module

The external clock and GPIO pins need to be exported out of Qsys system by declaring them as conduit interface in the spec. If SRAM is Avalon-mm slave, you just plug and play the master (make the connection) and the Avalon fabric will do the rest for you. One more thing you have to include an additional Avalon-mm slave control interface in your module that instruct how/when to transfer data from the memory.