Accessing SRAM from NIOS and Verilog Module

Thanks for the links!

So I used the custom master template and added it to my Qsys system. The user and control conduits are exported and so is the clock. The master is connected to the SRAM slave. As I understand it, I now instantiate this Qsys system in my top level verilog module and I can read out the data from 'user_read_buffer'. This doesn't seem to work when I try to display the data on to the LEDs. Is there something else I need to take care of when sharing the SRAM between NIOS and the hardware?