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Altera_Forum's avatar
Altera_Forum
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12 years ago

Absolute noob here, trying to design a serial countdown on four seven segment display

Hi all!

New to the forums, new to developing for FPGA's.

I have a quick question;

I am using the Altera cylcone V gx development board, which has 4 7-segment displays.

Here's what I want in sequence:

1) All 4 displays fully lit up.

2) First 7-segment turns off each segment (counts down) in a clockwise pattern (This works).

Here is where it doesn't work:

3) After first 7-segment block is off, second begins same countdown, then third, then fourth.

4) After all segments are off, then an LED display occurs (Not yet designed).

I am using a modification of the simple_counter design used in the training.

Is there some kind of item (I am REALLY new, so educate me on my lingo) that would allow me to accomplish this task?

Currently, I have a 12 bit mplex bus out, and the 4 segments are there, so obviously they are all doing it at the same time, but at different speeds.

I guess what I envision (But am probably wrong) is some kind of switch that says:

when counter1 reaches 3'b111, switch to new counter2.

same for counter2 to 3, etc, etc.

Any help would be greatly appreciated.

Thanks!

D

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    I guess what I envision (But am probably wrong) is some kind of switch that says:

    when counter1 reaches 3'b111, switch to new counter2.

    same for counter2 to 3, etc, etc.

    --- Quote End ---

    What's the problem? You only need to describe this behaviour in your Verilog code.

    It's a very simple task. Start writing some code and post it when you get stuck.

    We aren't supposed to do your homework ;-)
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Lol, thanks!

    It's not home work, I'm doing this on my own.

    I'll post what I've got so far soon.

    Thanks again,

    D
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Okay, here's what I've got: 

    
module binary1_to_led (
	// Create input from the clock.
	input  bin_counter,
	// Create output busses for the counters.
	output reg  counter_out); 
always @ *
	case (bin_counter)
		// output to Hex0
		3'b001 : counter_out = 7'b0000000;  //
		3'b010 : counter_out = 7'b0010000;  //
		3'b011 : counter_out = 7'b0011000;  //
		3'b100 : counter_out = 7'b0011100;  //
		3'b101 : counter_out = 7'b0011110;  //
		3'b110 : counter_out = 7'b1011110;  //
		3'b111 : counter_out = 7'b1111110;  //
		default : counter_out = 7'b1111111;
	endcase
endmodule// end of module counter

    I have four of these (counter_out->counter_out4) broken out in for different .v files.

    So, do I need to:

    1) Put all of the counter's in to one file.

    2) Create outputs for each counter_out

    3) Create some kind of a function that basically says:

    while not 3'b111

    do

    3'b001 : counter_out = 7'b0000000; //

    3'b010 : counter_out = 7'b0010000; //

    3'b011 : counter_out = 7'b0011000; //

    3'b100 : counter_out = 7'b0011100; //

    3'b101 : counter_out = 7'b0011110; //

    3'b110 : counter_out = 7'b1011110; //

    3'b111 : counter_out = 7'b1111110; //

    done

    default : counter_out = 7'b1111111;

    while not 3'b111

    do

    3'b001 : counter_out2 = 7'b0000000; //

    3'b010 : counter_out2 = 7'b0010000; //

    3'b011 : counter_out2 = 7'b0011000; //

    3'b100 : counter_out2 = 7'b0011100; //

    3'b101 : counter_out2 = 7'b0011110; //

    3'b110 : counter_out2 = 7'b1011110; //

    3'b111 : counter_out2 = 7'b1111110; //

    done

    default : counter_out2 = 7'b1111111; (<-- I don't think I can specify multiple defaults)

    etc, etc?

    Thanks,

    D
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Okay, here's my latest.

    The first 7 segment counts down, but the others don't appear to do anything. I think it's the way I am mapping the counter, or the count variable isn't adding up the way I think it should.

    Thanks in advance!

    D 

    
// Mapping down the seven segment LED to perform a clockwise "Predator"ish symbol countdown.
// 
//Begin Module
module whileBinary_to_led (
	// Create input from the clock.
	input  bin_counter,
	// Create output busses for the counters.
	output reg  counter_out,
	output reg  counter_out2,
	output reg  counter_out3,
	output reg  counter_out4); 
	integer count = 0;
	
always @ *
begin
	counter_out = 7'b0000000;
	counter_out2 = 7'b0000000;
	counter_out3 = 7'b0000000;
	counter_out4 = 7'b0000000;
	if (count <= 6) begin
		case (bin_counter)
			// output to Hex0
			3'b001 : counter_out = 7'b0000000;  //
			3'b010 : counter_out = 7'b0010000;  //
			3'b011 : counter_out = 7'b0011000;  //
			3'b100 : counter_out = 7'b0011100;  //
			3'b101 : counter_out = 7'b0011110;  //
			3'b110 : counter_out = 7'b1011110;  //
			3'b111 : counter_out = 7'b1111110;  //
			default : counter_out = 7'b1111111;
		endcase
	end
	
	if ((count > 6) && (count <= 13)) begin
		case (bin_counter)
			// output to Hex0
			3'b001 : counter_out2 = 7'b0000000;  //
			3'b010 : counter_out2 = 7'b0010000;  //
			3'b011 : counter_out2 = 7'b0011000;  //
			3'b100 : counter_out2 = 7'b0011100;  //
			3'b101 : counter_out2 = 7'b0011110;  //
			3'b110 : counter_out2 = 7'b1011110;  //
			3'b111 : counter_out2 = 7'b1111110;  //
			default : counter_out2 = 7'b1111111;
		endcase
	
	if ((count > 13) && (count <= 20))
		case (bin_counter)
			// output to Hex0
			3'b001 : counter_out3 = 7'b0000000;  //
			3'b010 : counter_out3 = 7'b0010000;  //
			3'b011 : counter_out3 = 7'b0011000;  //
			3'b100 : counter_out3 = 7'b0011100;  //
			3'b101 : counter_out3 = 7'b0011110;  //
			3'b110 : counter_out3 = 7'b1011110;  //
			3'b111 : counter_out3 = 7'b1111110;  //
			default : counter_out3 = 7'b1111111;
		endcase
	
	if ((count > 20) && (count <= 27))
		case (bin_counter)
			// output to Hex0
			3'b001 : counter_out4 = 7'b0000000;  //
			3'b010 : counter_out4 = 7'b0010000;  //
			3'b011 : counter_out4 = 7'b0011000;  //
			3'b100 : counter_out4 = 7'b0011100;  //
			3'b101 : counter_out4 = 7'b0011110;  //
			3'b110 : counter_out4 = 7'b1011110;  //
			3'b111 : counter_out4 = 7'b1111110;  //
			default : counter_out4 = 7'b1111111;
		endcase
	end
	count = count + 1;
end
endmodule// end of module counter
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    It seems that the counter is a) not counting, b) Being reset to 0 each loop, or c) the case statement is 'fing with it.

    D
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    First of all get rid of these assignments!!!

    counter_out = 7'b0000000;

    counter_out2 = 7'b0000000;

    counter_out3 = 7'b0000000;

    counter_out4 = 7'b0000000;

    You need them only at reset or, possibly, only when count==0.

    Remember that Verilog and VHDL are description languages, NOT programming languages. They are supposed to describe physical hardware like flip flops and logic gates where everything happens concurrently rather than sequentially.

    Then, you'd better use a clock toregister those counter_out values.

    always @ (posedge clk)

    ....

    case (bin_counter)

    ...

    3'b001 : counter_out <= 7'b0000000;

    ...