Forum Discussion
Altera_Forum
Honored Contributor
11 years agoOkay, here's what I've got:
module binary1_to_led (
// Create input from the clock.
input bin_counter,
// Create output busses for the counters.
output reg counter_out);
always @ *
case (bin_counter)
// output to Hex0
3'b001 : counter_out = 7'b0000000; //
3'b010 : counter_out = 7'b0010000; //
3'b011 : counter_out = 7'b0011000; //
3'b100 : counter_out = 7'b0011100; //
3'b101 : counter_out = 7'b0011110; //
3'b110 : counter_out = 7'b1011110; //
3'b111 : counter_out = 7'b1111110; //
default : counter_out = 7'b1111111;
endcase
endmodule// end of module counter I have four of these (counter_out->counter_out4) broken out in for different .v files. So, do I need to: 1) Put all of the counter's in to one file. 2) Create outputs for each counter_out 3) Create some kind of a function that basically says: while not 3'b111 do 3'b001 : counter_out = 7'b0000000; // 3'b010 : counter_out = 7'b0010000; // 3'b011 : counter_out = 7'b0011000; // 3'b100 : counter_out = 7'b0011100; // 3'b101 : counter_out = 7'b0011110; // 3'b110 : counter_out = 7'b1011110; // 3'b111 : counter_out = 7'b1111110; // done default : counter_out = 7'b1111111; while not 3'b111 do 3'b001 : counter_out2 = 7'b0000000; // 3'b010 : counter_out2 = 7'b0010000; // 3'b011 : counter_out2 = 7'b0011000; // 3'b100 : counter_out2 = 7'b0011100; // 3'b101 : counter_out2 = 7'b0011110; // 3'b110 : counter_out2 = 7'b1011110; // 3'b111 : counter_out2 = 7'b1111110; // done default : counter_out2 = 7'b1111111; (<-- I don't think I can specify multiple defaults) etc, etc? Thanks, D