Absolute noob here, trying to design a serial countdown on four seven segment display

First of all get rid of these assignments!!!

counter_out = 7'b0000000;

counter_out2 = 7'b0000000;

counter_out3 = 7'b0000000;

counter_out4 = 7'b0000000;

You need them only at reset or, possibly, only when count==0.

Remember that Verilog and VHDL are description languages, NOT programming languages. They are supposed to describe physical hardware like flip flops and logic gates where everything happens concurrently rather than sequentially.

Then, you'd better use a clock toregister those counter_out values.

always @ (posedge clk)

....

case (bin_counter)

...

3'b001 : counter_out <= 7'b0000000;

...