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Altera_Forum's avatar
Altera_Forum
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11 years ago

Absolute noob here, trying to design a serial countdown on four seven segment display

Hi all! New to the forums, new to developing for FPGA's. I have a quick question; I am using the Altera cylcone V gx development board, which has 4 7-segment displays. Here's what...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Okay, here's my latest.

The first 7 segment counts down, but the others don't appear to do anything. I think it's the way I am mapping the counter, or the count variable isn't adding up the way I think it should.

Thanks in advance!

D 


// Mapping down the seven segment LED to perform a clockwise "Predator"ish symbol countdown.
// 
//Begin Module
module whileBinary_to_led (
	// Create input from the clock.
	input  bin_counter,
	// Create output busses for the counters.
	output reg  counter_out,
	output reg  counter_out2,
	output reg  counter_out3,
	output reg  counter_out4); 
	integer count = 0;
	
always @ *
begin
	counter_out = 7'b0000000;
	counter_out2 = 7'b0000000;
	counter_out3 = 7'b0000000;
	counter_out4 = 7'b0000000;
	if (count <= 6) begin
		case (bin_counter)
			// output to Hex0
			3'b001 : counter_out = 7'b0000000;  //
			3'b010 : counter_out = 7'b0010000;  //
			3'b011 : counter_out = 7'b0011000;  //
			3'b100 : counter_out = 7'b0011100;  //
			3'b101 : counter_out = 7'b0011110;  //
			3'b110 : counter_out = 7'b1011110;  //
			3'b111 : counter_out = 7'b1111110;  //
			default : counter_out = 7'b1111111;
		endcase
	end
	
	if ((count > 6) && (count <= 13)) begin
		case (bin_counter)
			// output to Hex0
			3'b001 : counter_out2 = 7'b0000000;  //
			3'b010 : counter_out2 = 7'b0010000;  //
			3'b011 : counter_out2 = 7'b0011000;  //
			3'b100 : counter_out2 = 7'b0011100;  //
			3'b101 : counter_out2 = 7'b0011110;  //
			3'b110 : counter_out2 = 7'b1011110;  //
			3'b111 : counter_out2 = 7'b1111110;  //
			default : counter_out2 = 7'b1111111;
		endcase
	
	if ((count > 13) && (count <= 20))
		case (bin_counter)
			// output to Hex0
			3'b001 : counter_out3 = 7'b0000000;  //
			3'b010 : counter_out3 = 7'b0010000;  //
			3'b011 : counter_out3 = 7'b0011000;  //
			3'b100 : counter_out3 = 7'b0011100;  //
			3'b101 : counter_out3 = 7'b0011110;  //
			3'b110 : counter_out3 = 7'b1011110;  //
			3'b111 : counter_out3 = 7'b1111110;  //
			default : counter_out3 = 7'b1111111;
		endcase
	
	if ((count > 20) && (count <= 27))
		case (bin_counter)
			// output to Hex0
			3'b001 : counter_out4 = 7'b0000000;  //
			3'b010 : counter_out4 = 7'b0010000;  //
			3'b011 : counter_out4 = 7'b0011000;  //
			3'b100 : counter_out4 = 7'b0011100;  //
			3'b101 : counter_out4 = 7'b0011110;  //
			3'b110 : counter_out4 = 7'b1011110;  //
			3'b111 : counter_out4 = 7'b1111110;  //
			default : counter_out4 = 7'b1111111;
		endcase
	end
	count = count + 1;
end
endmodule// end of module counter