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Altera_Forum's avatar
Altera_Forum
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12 years ago

10G reference design - last timing violation is internal

Hello all.

Using the Altera Ethernet 10G Design Example in Qsys with Quartus 13.1.

This is part of a bigger build.

One timing violation persists and is indicated below and it is internal to the IP core so

not sure how to approach these internal violations when I know nothing about the core inners.

Thanks,

Cos

ten_g_fpga:ten_g_fpga_inst|ten_g_fpga_eth_10ginst_0:eth_10ginst_0|altera_xcvr_xaui:xaui|siv_xcvr_xaui:xaui_phy|hxaui:hxaui_0|hxaui_alt4gxb:use_device_family_siv_sv.hxaui_alt4gxb|hxaui_alt4gxb_alt4gxb_dksa:hxaui_alt4gxb_alt4gxb_dksa_component|wire_cent_unit0_dprioout

to

ten_g_fpga:ten_g_fpga_inst|ten_g_fpga_eth_10ginst_0:eth_10ginst_0|altera_xcvr_xaui:xaui|alt_xcvr_reconfig_siv:alt_xcvr_reconfig_0|alt_xcvr_reconfig_basic_tgx:sc_basic|alt_dprio:inst_alt_dprio|in_data_shift_reg[0]

Slack = -1.341

Relationship = 6.666

Skew = 0.132

Data Delay = 8.043

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    I had a similar timing error related problem when trying to reproduce a PCIe example design, and the solution there was to turn on multi-corner timing analysis and change the fitter effort to standard.

    You can also take a look at the "Chip Planner" view of the IP placement. For example, I had timing errors with a DDR3 design where I had two DDR interfaces and configured the design for PLL sharing (one as master, the other as slave). The DDR interfaces were on opposite sides of the device, so it was not surprising that I should not try to share PLL outputs ... once I turned off that setting (so that each DDR interface used its own PLL), the timing passed.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Thanks, Dave.

    No, the mentioned ideas are non-issues in the design.

    Ultimately, I expect that these example designs will not make timing in some cases

    and adjustments will be required.

    The question is what are some approaches to resolving "under-the-hood" timing violations.

    Be good if we had some Altera folks out there who know the design.

    Best,

    Cos
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    The question is what are some approaches to resolving "under-the-hood" timing violations.

    Be good if we had some Altera folks out there who know the design.

    --- Quote End ---

    I suspect that you will not get responses on this forum. I think Altera prefers those questions to go through their "Service Request" channels. Typically forum posters will file a SR and then post the response back on the forum if it was useful.

    Timing violations in black-box IP are pretty frustrating ... as are synthesis failures, obnoxious warning messages, etc etc ...

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thanks, Dave.

    I have had Altera types work on some issues through the forum so...

    FYI, looks like this is a cross partition boundary issue.

    A lot of documentation to go through on the topic.

    If I new the design then I would be inclined to register the signal as docs suggest.

    It would seem that the design is not coded well if I have to insert regs.

    Perhaps there is a needle-in-a-haystack fitter or synth setting to resolve.

    Thx,

    Cos
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    FYI, looks like this is a cross partition boundary issue.

    --- Quote End ---

    You can test this theory by telling TimeQuest each clock is exclusive/asynchronous

    set_clock_groups -exclusive -group clk1 -group clk2

    This stops TimeQuest from analyzing signals that cross between these two clock domains, and inherently makes you responsible for ensuring that you include synchronizers where needed.

    --- Quote Start ---

    If I new the design then I would be inclined to register the signal as docs suggest.

    --- Quote End ---

    If the example is inconsistent with the documentation, then its likely a poor example, and not worth copying further. You're better off to start with a new design, and then if you get stuck with it, post it and a simulation here, or file a Service Request with Altera.

    --- Quote Start ---

    Perhaps there is a needle-in-a-haystack fitter or synth setting to resolve.

    --- Quote End ---

    I have yet to find the "fix this poor example" button :)

    Cheers,

    Dave