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Altera_Forum
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11 years ago

10G reference design - last timing violation is internal

Hello all. Using the Altera Ethernet 10G Design Example in Qsys with Quartus 13.1. This is part of a bigger build. One timing violation persists and is indicated below and it is internal...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Thanks, Dave.

I have had Altera types work on some issues through the forum so...

FYI, looks like this is a cross partition boundary issue.

A lot of documentation to go through on the topic.

If I new the design then I would be inclined to register the signal as docs suggest.

It would seem that the design is not coded well if I have to insert regs.

Perhaps there is a needle-in-a-haystack fitter or synth setting to resolve.

Thx,

Cos