10G reference design - last timing violation is internal

I had a similar timing error related problem when trying to reproduce a PCIe example design, and the solution there was to turn on multi-corner timing analysis and change the fitter effort to standard.

You can also take a look at the "Chip Planner" view of the IP placement. For example, I had timing errors with a DDR3 design where I had two DDR interfaces and configured the design for PLL sharing (one as master, the other as slave). The DDR interfaces were on opposite sides of the device, so it was not surprising that I should not try to share PLL outputs ... once I turned off that setting (so that each DDR interface used its own PLL), the timing passed.

Cheers,

Dave