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Altera_Forum
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11 years ago

10G reference design - last timing violation is internal

Hello all. Using the Altera Ethernet 10G Design Example in Qsys with Quartus 13.1. This is part of a bigger build. One timing violation persists and is indicated below and it is internal...
Altera_Forum's avatar
Altera_Forum
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11 years ago

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The question is what are some approaches to resolving "under-the-hood" timing violations.

Be good if we had some Altera folks out there who know the design.

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I suspect that you will not get responses on this forum. I think Altera prefers those questions to go through their "Service Request" channels. Typically forum posters will file a SR and then post the response back on the forum if it was useful.

Timing violations in black-box IP are pretty frustrating ... as are synthesis failures, obnoxious warning messages, etc etc ...

Cheers,

Dave