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Altera_Forum
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11 years ago

10G reference design - last timing violation is internal

Hello all. Using the Altera Ethernet 10G Design Example in Qsys with Quartus 13.1. This is part of a bigger build. One timing violation persists and is indicated below and it is internal...
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Altera_Forum
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11 years ago

Thanks, Dave.

No, the mentioned ideas are non-issues in the design.

Ultimately, I expect that these example designs will not make timing in some cases

and adjustments will be required.

The question is what are some approaches to resolving "under-the-hood" timing violations.

Be good if we had some Altera folks out there who know the design.

Best,

Cos