Verify Failed

luisalba,

I have had a similar problem. I believe it has to do with my trace lengths on my JTAG lines. We have a couple of custom boards now, the last 2 I have interfaced with the USB cable and latest versions of Quartus.

With one of our boards, shorter trace lengths, I have no problems at all. With the other, I run into problems when trying to load large programs into SDRAM. Although, my flash programmer works just fine. I can also write to the FPGA without a hitch, as well as the configuration device. I only have problems loading programs to SDRAM.

For this project try using your old ByteBlasterMV. This is a slower device and works just fine for me.

When you lay out your next board, give those JTAG lines a little more attention.

Doug

Thanks for your quick response.

I only have USB Blaster(so not the possibility of ByteBlaster), but I'm still wondering why these problems with JTAG appear only with the new versions of Quartus and NIOS, because with Quartus 4.2 and Nios 1.1 I don't have any problem??

Any idea??

Thanks a lot,

Luis

Hello,

I posted below on another thread but it looks pertinent here as well so I thought I would put in my two cents. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

Just a note:We made a custom cable and emulated ByteBlaster II with on-board circuitry.Even though Altera recommends USB Rev B I believe for debugging , this works well enough.

Regards,

-Baycool

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Hello all,

I am re-releasing a custom development board that was running with 5.0(FULL) now with 5.1(Web).

I get the infamous:

Verify failed

Leaving target processor paused

Normally, I would also suspect hardware as a first option. However, I switched PCs and re-ran my 5.0(FULL) and my development board is working fine. So Hardware IS NOT ALWAYS A CULPRIT HERE.

What I did to port 5.0 Full to 5.1(Web)

1. Delete old NiosII Core 5.0 (Licensed) and insert time-limited 5.1 core(Reset my processorrs characteristics : fast, no tightly coupled memory, etc.)

2. Loaded Virgin machine with 5.1(Web) , 5.1(Megacores) and NiosII5.1 eval(time-limited)

3. Had to edit qsf because I had incremental compiles set and Web5.1 does not support.

So now with 5.1 (Web)

-Recompile worked fine.

-Program of device successful

Run SW

-SYSID verification okay

- Get Processor paused message( Verify Failed)

Any thoughts?

Thanks,

-Baycool

Hi all,

I had the same verification problems while working with an UP3-Development Board. There the problem was caused by an incorrect SDRAM-Timing.

But there also a lot of other threads, dealing with this problem. May be it&#39;s interesting to know, that the verification function can be turned off. Just search this forum for "no-verify". There a guy explained how to turn off this feature.

--- Quote Start ---

originally posted by luisalba@Nov 11 2005, 01:42 PM

hello everybody.

i&#39;m having problems with a custom board. using quartus 4.2 and nios1.1 everything works fine. i decided to move to quartus 5.01 and nios ii 5.01 and the same projects that worked correctly with the old version failed with the new one:

using cable "usb-blaster [usb-1]", device 1, instance 0x00

pausing target processor: ok

reading system id at address 0x021208b8: verified

downloading 03000020 ( 0%)

downloading 03010000 (74%)

downloaded 86kb in 1.1s (78.1kb/s)

verifying 03000020 ( 0%)

verify failed

leaving target processor paused

almost always i get this error and i really don&#39;t know why. ther is sdram at 3000020, but i think the sdram is not the problem because with the old version everything worked fine.

have someone had the same problem before? please help!!

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=10929)

--- quote end ---

--- Quote End ---

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/laugh.gif

Hi luisalba i&#39;m getting started now with a stratix II (EP2S60F1020C4) and i had the same problem :

Verifying 03000020 ( 0%)

Verify failed

Leaving target processor paused.

I solved it by downloading an the board the standard.qpf file that i found i the directory:

altera\kits\StratixII_DSP_Kit-v1.1.0\Examples\HW\NiosII\example_designs\vhdl\standard

I have downloaded this file without compiling it.

I started Nios II IDE and runned a sample project unchecking Validate Nios II System ID before software downolad.

Everything works fine now.Good Luck and sorry if said incorrect things but i&#39;m not so expert as you! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif

--- Quote Start ---

originally posted by rj043@Nov 30 2005, 06:35 AM

hi all,

i had the same verification problems while working with an up3-development board. there the problem was caused by an incorrect sdram-timing.

but there also a lot of other threads, dealing with this problem. may be it&#39;s interesting to know, that the verification function can be turned off. just search this forum for "no-verify". there a guy explained how to turn off this feature.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=11265)

--- quote end ---

--- Quote End ---

I have encountered this problem many times, most of the cases are caused by the RAM of NiosII, I mean the sram, sdram etc.

First of all, be sure that your ram working properly

--- Quote Start ---

originally posted by luisalba@Nov 11 2005, 09:42 PM

hello everybody.

i&#39;m having problems with a custom board. using quartus 4.2 and nios1.1 everything works fine. i decided to move to quartus 5.01 and nios ii 5.01 and the same projects that worked correctly with the old version failed with the new one:

using cable "usb-blaster [usb-1]", device 1, instance 0x00

pausing target processor: ok

reading system id at address 0x021208b8: verified

downloading 03000020 ( 0%)

downloading 03010000 (74%)

downloaded 86kb in 1.1s (78.1kb/s)

verifying 03000020 ( 0%)

verify failed

leaving target processor paused

almost always i get this error and i really don&#39;t know why. ther is sdram at 3000020, but i think the sdram is not the problem because with the old version everything worked fine.

have someone had the same problem before? please help!!

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=10929)

--- quote end ---

--- Quote End ---

I have the same problem with you! And if has troubled me a long time,but I don&#39;t kown how to resolve it.

somebody said that it was "the phase shit" about sdram and system,but when I set the sdram‘s phase earlier than the system&#39;s 27 rad,it didn&#39;t work either.

I also wish someone can give us a help! Thanks!

Hmm I have similar problem here.

I was able to compile and run the &#39;custom instruction tutorial&#39; with version 5.0 QuartusII and NiosII.

Now I removed them and install version 5.1 of QuartusII and NiosII.

With the same project, I am keep getting below message.

I am using UP3 Board with Cyclone device.

I didn&#39;t use SDRAM, I am using SRAM only.

Does anybody have idea?

Using cable "ByteBlasterII [LPT1]", device 1, instance 0x00

Pausing target processor: OK

Reading System ID at address 0x00020848: verified

Downloading 00000000 ( 0%)

Downloaded 54KB in 1.1s (49.0KB/s)

Verifying 00000000 ( 0%)

Verify failed between address 0x0 and 0xD663

Leaving target processor paused