Verify Failed

Hello,

I posted below on another thread but it looks pertinent here as well so I thought I would put in my two cents. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

Just a note:We made a custom cable and emulated ByteBlaster II with on-board circuitry.Even though Altera recommends USB Rev B I believe for debugging , this works well enough.

Regards,

-Baycool

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Hello all,

I am re-releasing a custom development board that was running with 5.0(FULL) now with 5.1(Web).

I get the infamous:

Verify failed

Leaving target processor paused

Normally, I would also suspect hardware as a first option. However, I switched PCs and re-ran my 5.0(FULL) and my development board is working fine. So Hardware IS NOT ALWAYS A CULPRIT HERE.

What I did to port 5.0 Full to 5.1(Web)

1. Delete old NiosII Core 5.0 (Licensed) and insert time-limited 5.1 core(Reset my processorrs characteristics : fast, no tightly coupled memory, etc.)

2. Loaded Virgin machine with 5.1(Web) , 5.1(Megacores) and NiosII5.1 eval(time-limited)

3. Had to edit qsf because I had incremental compiles set and Web5.1 does not support.

So now with 5.1 (Web)

-Recompile worked fine.

-Program of device successful

Run SW

-SYSID verification okay

- Get Processor paused message( Verify Failed)

Any thoughts?

Thanks,

-Baycool