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Honored Contributor
Honored ContributorSurprised to get "converted into an equivalent circuit" warning
Hi Folks-
I have a Verlog delay line module that seems straightforward and seems to work when I simulate it using ModelSim and when realized on my Cyclone II FPGA. I always get warning 13310 for every bit in the delay line array:
Warning (13310): Register "MPS_SOPC:inst|pulse_engine_0:the_pulse_engine_0|pulse_engine:pulse_engine_0|sample_delay:delay|mem" is converted into an equivalent circuit using register "MPS_SOPC:inst|pulse_engine_0:the_pulse_engine_0|pulse_engine:pulse_engine_0|sample_delay:delay|mem~_emulated" and latch "MPS_SOPC:inst|pulse_engine_0:the_pulse_engine_0|pulse_engine:pulse_engine_0|sample_delay:delay|mem~latch"
`define BUFFER_SIZE 64
module sample_delay(
input wire reset_n, // Reset
input wire adc_clock, // Sample clock
input wire adc_data, // Input sample
output wire adc_data_delayed // Delayed sample
);
reg mem;
integer i;
initial
begin
for(i = 0; i < `BUFFER_SIZE; i = i + 1) mem = 14'd0;
end
assign adc_data_delayed = mem;
always @(posedge adc_clock or negedge reset_n)
begin
if(~reset_n)
begin
for(i = 0; i < `BUFFER_SIZE; i = i + 1) mem <= adc_data;
end
else
begin
mem <= adc_data; // <--- COMPLAINS HERE AND NEXT LINE
for(i = 1; i < `BUFFER_SIZE; i = i + 1) mem <= mem;
end
end
endmodule
