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Altera_Forum
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15 years ago

Surprised to get "converted into an equivalent circuit" warning

Hi Folks- I have a Verlog delay line module that seems straightforward and seems to work when I simulate it using ModelSim and when realized on my Cyclone II FPGA. I always get warning 13310 f...
Altera_Forum's avatar
Altera_Forum
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15 years ago

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Maybe sligthly Off Topic but I strongly disagree with the use of the "initial" statement for synthesizable designs.

Don't you think this is a dangerous way of describing circuits?

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I half agree with you. Before I started this thread, I was told by a local expert (and believed it) that the "initial" statement was not synthesizable but useful for simulation. Based on that understanding, I leave the "initial" statements in so I can resimulate if necessary. I assumed it had no effect on synthesis.

The comments in this thread have shown me that the "initial" statement does have some indirect bearing on how the tool behaves. It might not make a bit of difference in the final synthesized output though. I have no idea how to prove or disprove that.

JJS