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Altera_Forum
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15 years ago

Surprised to get "converted into an equivalent circuit" warning

Hi Folks- I have a Verlog delay line module that seems straightforward and seems to work when I simulate it using ModelSim and when realized on my Cyclone II FPGA. I always get warning 13310 f...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Maybe sligthly Off Topic but I strongly disagree with the use of the "initial" statement for synthesizable designs.

Don't you think this is a dangerous way of describing circuits?