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Altera_Forum
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15 years ago

Surprised to get "converted into an equivalent circuit" warning

Hi Folks- I have a Verlog delay line module that seems straightforward and seems to work when I simulate it using ModelSim and when realized on my Cyclone II FPGA. I always get warning 13310 f...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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i think the power-up values from the initial block disagree with the values from your reset, causing the latch. this is why changing the reset values from adc_data to 0 fixes the issue

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Thanks. That was the key to making the warnings go away. I'm amazed at the deductions that Quartus is making when it analyzes the HDL code. I wonder if it ever misses the intent.

My inexperience is obviously exposed. It's such a complex tool and there is clearly no substitute for experience and knowledge. I hope to acquire both over the years.

Thanks to everyone for your opinions and help.

JJS