I am still dealing with problems of unknown nature on my custom board. Maybe somebody will have a bright idea how to move forward a little: My custom board based on Cyclone C6 consist of internal 4k ram (int_ram), external CFI flash, external SRAM (both on the same Avalon tri-state bus). I have prepared a small hosted C-code to run SRAM memory test and flash some LEDs to show progress and the test results... Code is tested and works ok. When I build NIOS II to boot from an EPCS controler or an external CFI Flash but execute from int_ram everything is fine. My code works great, goes throug the SRAM memory test routine and test ends with a success. From this experiment I would find: 1. CFI flash is configured correctly because: - I can erase it, program it and verify it with no errors - I can store the my code and copiero code there - I can run copier program from CFI Flash fine - I can copy code from CFI Flash to int_ram and it works ok 2. My SRAM is configured correctly because: - my C-code goes through all SRAM addresses and reads 32-bits patterns of aaa.../555... previously written - my C-code goes through "walking 1s" routine for each SRAM address and it checks out ok. but... When I build NIOS II to boot from external CFI Flash and execute from there, my code does not work. It does not matter if I link .rodata and .rwdata partitions to go into int_ram or SRAM - it does not work. When I build NIOS II to boot from external CFI Flash and execute from external SRAM, my code does not work. I am confused here: CFI Flash tested ok, SRAM tested ok but when I am trying to run my code hosted in these devices everything falls apart. When am I missing here? BTW - My code skips first 10k of 1Mb SRAM when operates from the same memory to not overwrite itself but tests whole SRAM memory when operates from int_ram. I have also tried slowing down the cpu clock to avoid SRAM timing issues. Nothing helps.

Okay, let&#39;s get the "is it plugged in?" steuff out of the way... Is the Avalon Tristate bus slave connected to the instruction master on the Nios II CPU as well as the data master? Does the data master have priority over the instruction master? With the pipelining, it may be trying to fetch something before it gets written out. Also, in the Nios II Software Developer&#39;s Handbook, on page 7-5 there&#39;s a section "Writing Program Loaders or Self-Modifying Code." It might be useful, since what you describe also sounds like it&#39;s not seeing the instructions in question in the instruction cache, or they haven&#39;t flushed from the data cache to the external memory yet. The section on "Bit 31 cache memory bypass" may be useful, too. Just some guesses. Good luck!

--- Quote Start --- originally posted by mike desimone@Jul 22 2004, 09:51 AM okay, let&#39;s get the "is it plugged in?" steuff out of the way... --- Quote End --- Yes, please do not be afraid to ask basic questions - I am new here, I make a lot of stupid mistakes all the time... <div class='quotetop'>QUOTE </div> --- Quote Start --- Is the Avalon Tristate bus slave connected to the instruction master on the Nios II CPU as well as the data master?[/b] --- Quote End --- Yes and... Yes. It was this way by default http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif ...but honestly, I did not check this before - thank you. <div class='quotetop'>QUOTE </div> --- Quote Start --- Does the data master have priority over the instruction master? With the pipelining, it may be trying to fetch something before it gets written out.[/b] --- Quote End --- This I am not sure - how to check these priorities? As you can see, they probably are how they are set by default, did not changed them. <div class='quotetop'>QUOTE </div> --- Quote Start --- Also, in the Nios II Software Developer&#39;s Handbook, on page 7-5 there&#39;s a section "Writing Program Loaders or Self-Modifying Code." It might be useful, since what you describe also sounds like it&#39;s not seeing the instructions in question in the instruction cache, or they haven&#39;t flushed from the data cache to the external memory yet. The section on "Bit 31 cache memory bypass" may be useful, too.[/b] --- Quote End --- Should I be concerned with this issue if I use Nios II/e version, without cache memories? But this was good question - it could prove my C-code memory test was flawed if it worked from cache memory without flushing data to external SRAM... Since I am using NiosII/e I assume every memory cycle actually goes to the external memory without passing through cache systems, am I correct or not? Thanks for trying to help, I would appreciate any other ideas I can check, even the craziest ones http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif

Hi Pszemol, From the description of your system & the tests you&#39;ve completed I think you&#39;re very close... from what I gather reading your test setup, though, I am thinking that this may be a timing-related issue. This hypothesis comes from the fact that you can successfully complete a write/readback test using the CPU (data master). During such tests, the actual reads/writes to SRAM are not consecutive... that, is the assembly code actually running is probably not consecutive LD, LD, LD, LD, ST, ST, ST, etc. Additionally, the Nios CPU (Nios I and Nios II)&#39;s data master is not "latency aware".. so when it does an access and is told to &#39;wait&#39; by Avalon, it will not issue any more bus requests. This architecture works fine for data operations as (above), data read/writes are usually not consecutive. however, the CPU instruction master is different... when it is fetching instructions from memory the bus requests are often one per clock cycle. As such, the instruction master is designed to be "latency aware" (by the way, the Avalon bus spec discusses latency). This means that the master pipelines its request, even if the slave has wait states. This works great for SRAM as (depending on the clock speed), you can potentially get one instruction per clock cycle once the first few instructions are fetched. What this all means is that executing from SRAM, or doing a similar operation (DMA transfer) stresses the timing much more than just doing a memory read/write test with the CPU. If you have not done so already, it may be a good idea to double check the timing specs for the SRAM you&#39;re using against what is setup in SOPC Builder in your interface. Additionally, you might consider temporarily slowing clock speed to see if that helps, or just adding additional delay (setup/hold/wait) in the interface to user logic. Finally, one additional test which may be useful: go into the Quartus floor plan view of your design and look at the tri-state bus pins going off to SRAM. Ensure that the register that is feeding/being fed by that I/O cell are going to the register in the I/O cell, and not going across the chip (the I/O cell registers are the little square boxes in the floor plan view that are joined to the I/O..). Our tri-state bridge logic is designed to put registers into the I/O to minimize delay in going off-chip, but there have been some reports that Q4.0 SP1 was not doing this as it should (the user can always force the registers into the I/O cell via quartus assignment). If this last issue is part of the problem, feel free to contact me and I can discuss it with you further.

Thanks for these suggestions, Jesse - I will double check timings but something bothers me in this "timing" hypothesis: Notice - my code does not work not only when executed from SRAM but it also does not work directly from CFI flash. In the successful scenario, when I execute my code out of internal ram, where it was copied from CFI flash, the copier program has been added automaticaly in front of my code by the nios linker. In this case the code worked great so the copier was able to run directly from CFI Flash and copy succesfuly content of the memory into internal ram - why my code has problems with running from the same CFI flash? Also, I have actually slowed down the cpu clock already to check timing is not an issue here - forgot to mention this before - I added frequency divider in front of it, so instead of running full speed (18.88MHz) it run 2 times slower. It did not help with my 70ns SRAM chips, but right now I plan to play a little more with timing and maybe I will hit the sweet spot and start from there... I am affraid I could have several different issues with multiple symptoms in this design http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif How to sort things up - I am not sure...

--- Quote Start --- originally posted by pszemol@Jul 22 2004, 10:39 AM <div class='quotetop'>quote --- quote end --- --- quote start --- does the data master have priority over the instruction master? --- Quote End --- This I am not sure - how to check these priorities? As you can see, they probably are how they are set by default, did not changed them.[/b] --- Quote End --- In SOPC Builder, select "Show Arbitration Priorities" in the "View" menu. The bus connection dots get replaced by the priority numbers for each master for a given slave. By default, they are equal. I&#39;m not sure how it arbitrates when it&#39;s equal.

Still having strange problems with SRAM and FLASH

14 Replies

Altera_Forum
Honored Contributor
21 years ago
Okay, let's get the "is it plugged in?" steuff out of the way...

Is the Avalon Tristate bus slave connected to the instruction master on the Nios II CPU as well as the data master? Does the data master have priority over the instruction master? With the pipelining, it may be trying to fetch something before it gets written out.

Also, in the Nios II Software Developer's Handbook, on page 7-5 there's a section "Writing Program Loaders or Self-Modifying Code." It might be useful, since what you describe also sounds like it's not seeing the instructions in question in the instruction cache, or they haven't flushed from the data cache to the external memory yet. The section on "Bit 31 cache memory bypass" may be useful, too.

Just some guesses. Good luck!
Altera_Forum
Honored Contributor
21 years ago
--- Quote Start ---
originally posted by mike desimone@Jul 22 2004, 09:51 AM
okay, let's get the "is it plugged in?" steuff out of the way...
--- Quote End ---
Yes, please do not be afraid to ask basic questions - I am new here, I make a lot of stupid mistakes all the time...

<div class='quotetop'>QUOTE </div>
--- Quote Start ---
Is the Avalon Tristate bus slave connected to the instruction master on the Nios II CPU as well as the data master?[/b]
--- Quote End ---
Yes and... Yes. It was this way by default http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif ...but honestly, I did not check this before - thank you.

<div class='quotetop'>QUOTE </div>
--- Quote Start ---
Does the data master have priority over the instruction master? With the pipelining, it may be trying to fetch something before it gets written out.[/b]
--- Quote End ---
This I am not sure - how to check these priorities? As you can see, they probably are how they are set by default, did not changed them.

<div class='quotetop'>QUOTE </div>
--- Quote Start ---
Also, in the Nios II Software Developer's Handbook, on page 7-5 there's a section "Writing Program Loaders or Self-Modifying Code." It might be useful, since what you describe also sounds like it's not seeing the instructions in question in the instruction cache, or they haven't flushed from the data cache to the external memory yet. The section on "Bit 31 cache memory bypass" may be useful, too.[/b]
--- Quote End ---
Should I be concerned with this issue if I use Nios II/e version, without cache memories? But this was good question - it could prove my C-code memory test was flawed if it worked from cache memory without flushing data to external SRAM... Since I am using NiosII/e I assume every memory cycle actually goes to the external memory without passing through cache systems, am I correct or not?

Thanks for trying to help, I would appreciate any other ideas I can check, even the craziest ones http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif
Altera_Forum
Honored Contributor
21 years ago
Hi Pszemol,

From the description of your system & the tests you've completed I think you're very close... from what I gather reading your test setup, though, I am thinking that this may be a timing-related issue. This hypothesis comes from the fact that you can successfully complete a write/readback test using the CPU (data master).

During such tests, the actual reads/writes to SRAM are not consecutive... that, is the assembly code actually running is probably not consecutive LD, LD, LD, LD, ST, ST, ST, etc. Additionally, the Nios CPU (Nios I and Nios II)'s data master is not "latency aware".. so when it does an access and is told to 'wait' by Avalon, it will not issue any more bus requests. This architecture works fine for data operations as (above), data read/writes are usually not consecutive.

however, the CPU instruction master is different... when it is fetching instructions from memory the bus requests are often one per clock cycle. As such, the instruction master is designed to be "latency aware" (by the way, the Avalon bus spec discusses latency). This means that the master pipelines its request, even if the slave has wait states. This works great for SRAM as (depending on the clock speed), you can potentially get one instruction per clock cycle once the first few instructions are fetched.

What this all means is that executing from SRAM, or doing a similar operation (DMA transfer) stresses the timing much more than just doing a memory read/write test with the CPU.

If you have not done so already, it may be a good idea to double check the timing specs for the SRAM you're using against what is setup in SOPC Builder in your interface. Additionally, you might consider temporarily slowing clock speed to see if that helps, or just adding additional delay (setup/hold/wait) in the interface to user logic. Finally, one additional test which may be useful: go into the Quartus floor plan view of your design and look at the tri-state bus pins going off to SRAM. Ensure that the register that is feeding/being fed by that I/O cell are going to the register in the I/O cell, and not going across the chip (the I/O cell registers are the little square boxes in the floor plan view that are joined to the I/O..). Our tri-state bridge logic is designed to put registers into the I/O to minimize delay in going off-chip, but there have been some reports that Q4.0 SP1 was not doing this as it should (the user can always force the registers into the I/O cell via quartus assignment). If this last issue is part of the problem, feel free to contact me and I can discuss it with you further.
Altera_Forum
Honored Contributor
21 years ago
Thanks for these suggestions, Jesse - I will double check timings but something bothers me in this "timing" hypothesis:

Notice - my code does not work not only when executed from SRAM but it also does not work directly from CFI flash.

In the successful scenario, when I execute my code out of internal ram, where it was copied from CFI flash, the copier program has been added automaticaly in front of my code by the nios linker. In this case the code worked great so the copier was able to run directly from CFI Flash and copy succesfuly content of the memory into internal ram - why my code has problems with running from the same CFI flash?

Also, I have actually slowed down the cpu clock already to check timing is not an issue here - forgot to mention this before - I added frequency divider in front of it, so instead of running full speed (18.88MHz) it run 2 times slower. It did not help with my 70ns SRAM chips, but right now I plan to play a little more with timing and maybe I will hit the sweet spot and start from there...

I am affraid I could have several different issues with multiple symptoms in this design http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif How to sort things up - I am not sure...
Altera_Forum
Honored Contributor
21 years ago
--- Quote Start ---
originally posted by pszemol@Jul 22 2004, 10:39 AM
<div class='quotetop'>quote
--- quote end ---

--- quote start ---
does the data master have priority over the instruction master?
--- Quote End ---
This I am not sure - how to check these priorities? As you can see, they probably are how they are set by default, did not changed them.[/b]
--- Quote End ---

In SOPC Builder, select "Show Arbitration Priorities" in the "View" menu. The bus connection dots get replaced by the priority numbers for each master for a given slave. By default, they are equal. I'm not sure how it arbitrates when it's equal.
Altera_Forum
Honored Contributor
21 years ago
<div class='quotetop'>QUOTE </div>
--- Quote Start ---
Thanks for these suggestions, Jesse - I will double check timings [..]
Also, I have actually slowed down the cpu clock already to check timing is not an issue here - forgot to mention this before - I added frequency divider in front of it, so instead of running full speed (18.88MHz) it run 2 times slower. It did not help with my 70ns SRAM chips, but right now I plan to play a little more with timing and maybe I will hit the sweet spot and start from there...[/b]
--- Quote End ---
Jesse - you were right. It looks like it is a timing issue and a serious one. I have dismissed this too quickly based on my "divide clock by 2" test. I divided by 4 and it still did not do good, but then just for giggles I have divided by 8 and I got it working in some memory combination.

It still does NOT work when my .reset partition is assigned to my CFI flash and .exception, .text, .rodata, .rwdata are assigned to my SRAM but it works when I boot cpu from EPCS and execute code from SRAM or when I boot from CFI flash and execute code from the internal ram. Somehow it still does not like it when I want to rely completely on my external bus for both: booting from CFI flash and executing from SRAM. any ideas what could be the reason for this symptoms?

I have to go back to my books and re-read sections about Avalon bus timings, but at least I can see a small light at the end of the tunnel now http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif Thanks!
Altera_Forum
Honored Contributor
21 years ago
Hi, I had a lot of fun with an external 8 Bit slave device, until I found
the page 100 "Connection to External Devices" in "Avalon Bus Specification".

What is the databus widh of your external SRAM ?
How are the address lines connected to your SRAM ?
Altera_Forum
Honored Contributor
21 years ago
--- Quote Start ---
originally posted by fischer@Jul 22 2004, 07:09 PM
hi, i had a lot of fun with an external 8 bit slave device, until i found
the page 100 "connection to external devices" in "avalon bus specification".

what is the databus widh of your external sram ?
how are the address lines connected to your sram ?
--- Quote End ---

Very interesting... I read this and it was clear back then, now it is not so clear. Let me go through this with you guys:
- my Avalon slave port databus size is 16-bit for my flash and SRAM
- the address bus coming out from nios CPU currently is ext_memory_bus_addres[22..0] and is labeled CPU_A[22..0]
- memory map for my CFI flash in SOPC is from 0x00000000 to 0x007FFFFF, which makes the correct amount of 8M bytes (4M x 16 bit words)
- signal CPU_A[0] does not even go outside the FPGA
- signal CPU_A[1] is connected to the pin A0 of the flash and SRAM.

In my SOPC Builder, in the CFI Flash config, I have selected address bus width to be 22 bits, because my flash chip has pins A0-A21 which makes 22 bits. For User Logic handling SRAM I have configured address bus to be 18 bits wide because my SRAM chips have pins A0-A17.

Acording to the Avalon doc, for native aligment I should connect pins differently - CPU_A[2] to my A0 memory pins. Is it right? Something is not right, since with this I will miss one address line from the top - MSB on my cpu is CPU_A[22] and now it is connected to the A21 pin of my flash memory chip...

I use single AM29LV640MH-112RE for my flash and three IS62WV51216BLL-70TI as my SRAM.

I am puzzled. What am I missing here? What have I configured incorrectly? How to deal with this Avalon Documentation and A[2] issue?

Anyway, even if I have misconfigured A0 pin, should it affect the available memory size only? Since my code is small (less than 4k) it should not only work regardless of the A0 assigment (wrong assigment would cut the size of my memory in half) but also wrong assigment would cause my C-code memory test to fail... but is it passing ok - maybe I have some bug in my test memory C-code? - not so sure about that anymore... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif
Altera_Forum
Honored Contributor
21 years ago
--- Quote Start ---
originally posted by pszemol@Jul 23 2004, 10:33 AM
acording to the avalon doc, for native aligment i should connect pins differently - cpu_a[2] to my a0 memory pins. is it right? something is not right, since with this i will miss one address line from the top - msb on my cpu is cpu_a[22] and now it is connected to the a21 pin of my flash memory chip...
--- Quote End ---
Ooh! I use DYNAMIC alignment for memory, not native - I messed up alignment types.
So I guess I am good in this part of the issue http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif My CPU_A[1] goes correctly to A0 of memory chips http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/laugh.gif
Altera_Forum
Honored Contributor
21 years ago
Yeah!

Forum Discussion

Still having strange problems with SRAM and FLASH

14 Replies

Recent Discussions

NiosV µC/OS-II

AshlingRISCFree IDE Build system: 'source directory does not appear to contain CMakeLists.txt"

Recommended Quartus Prime Standard Edition for Nios V Development on MAX 10 FPGA (10M25DAF4817G)

Nios-V on Cyclone IV

Debug Know-How: Ashling* RiscFree* NIOS® V debug using Command Line