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originally posted by mike desimone@Jul 22 2004, 09:51 AM
okay, let's get the "is it plugged in?" steuff out of the way... --- Quote End ---
Yes, please do not be afraid to ask basic questions - I am new here, I make a lot of stupid mistakes all the time...
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Is the Avalon Tristate bus slave connected to the instruction master on the Nios II CPU as well as the data master?[/b]
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Yes and... Yes. It was this way by default
http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif ...but honestly, I did not check this before - thank you.
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Does the data master have priority over the instruction master? With the pipelining, it may be trying to fetch something before it gets written out.[/b]
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This I am not sure - how to check these priorities? As you can see, they probably are how they are set by default, did not changed them.
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Also, in the Nios II Software Developer's Handbook, on page 7-5 there's a section "Writing Program Loaders or Self-Modifying Code." It might be useful, since what you describe also sounds like it's not seeing the instructions in question in the instruction cache, or they haven't flushed from the data cache to the external memory yet. The section on "Bit 31 cache memory bypass" may be useful, too.[/b]
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Should I be concerned with this issue if I use Nios II/e version, without cache memories? But this was good question - it could prove my C-code memory test was flawed if it worked from cache memory without flushing data to external SRAM... Since I am using NiosII/e I assume every memory cycle actually goes to the external memory without passing through cache systems, am I correct or not?
Thanks for trying to help, I would appreciate any other ideas I can check, even the craziest ones
http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif
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