Forum Discussion
Altera_Forum
Honored Contributor
21 years ago --- Quote Start --- originally posted by fischer@Jul 22 2004, 07:09 PM hi, i had a lot of fun with an external 8 bit slave device, until i found
the page 100 "connection to external devices" in "avalon bus specification".
what is the databus widh of your external sram ?
how are the address lines connected to your sram ? --- Quote End --- Very interesting... I read this and it was clear back then, now it is not so clear. Let me go through this with you guys: - my Avalon slave port databus size is 16-bit for my flash and SRAM - the address bus coming out from nios CPU currently is ext_memory_bus_addres[22..0] and is labeled CPU_A[22..0] - memory map for my CFI flash in SOPC is from 0x00000000 to 0x007FFFFF, which makes the correct amount of 8M bytes (4M x 16 bit words) - signal CPU_A[0] does not even go outside the FPGA - signal CPU_A[1] is connected to the pin A0 of the flash and SRAM. In my SOPC Builder, in the CFI Flash config, I have selected address bus width to be 22 bits, because my flash chip has pins A0-A21 which makes 22 bits. For User Logic handling SRAM I have configured address bus to be 18 bits wide because my SRAM chips have pins A0-A17. Acording to the Avalon doc, for native aligment I should connect pins differently - CPU_A[2] to my A0 memory pins. Is it right? Something is not right, since with this I will miss one address line from the top - MSB on my cpu is CPU_A[22] and now it is connected to the A21 pin of my flash memory chip... I use single AM29LV640MH-112RE for my flash and three IS62WV51216BLL-70TI as my SRAM. I am puzzled. What am I missing here? What have I configured incorrectly? How to deal with this Avalon Documentation and A[2] issue? Anyway, even if I have misconfigured A0 pin, should it affect the available memory size only? Since my code is small (less than 4k) it should not only work regardless of the A0 assigment (wrong assigment would cut the size of my memory in half) but also wrong assigment would cause my C-code memory test to fail... but is it passing ok - maybe I have some bug in my test memory C-code? - not so sure about that anymore... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif