Honored Contributor
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--- Quote Start --- Thanks for these suggestions, Jesse - I will double check timings [..] Also, I have actually slowed down the cpu clock already to check timing is not an issue here - forgot to mention this before - I added frequency divider in front of it, so instead of running full speed (18.88MHz) it run 2 times slower. It did not help with my 70ns SRAM chips, but right now I plan to play a little more with timing and maybe I will hit the sweet spot and start from there...[/b] --- Quote End --- Jesse - you were right. It looks like it is a timing issue and a serious one. I have dismissed this too quickly based on my "divide clock by 2" test. I divided by 4 and it still did not do good, but then just for giggles I have divided by 8 and I got it working in some memory combination. It still does NOT work when my .reset partition is assigned to my CFI flash and .exception, .text, .rodata, .rwdata are assigned to my SRAM but it works when I boot cpu from EPCS and execute code from SRAM or when I boot from CFI flash and execute code from the internal ram. Somehow it still does not like it when I want to rely completely on my external bus for both: booting from CFI flash and executing from SRAM. any ideas what could be the reason for this symptoms? I have to go back to my books and re-read sections about Avalon bus timings, but at least I can see a small light at the end of the tunnel now http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif Thanks!
