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originally posted by pszemol@Jul 23 2004, 10:33 AM
acording to the avalon doc, for native aligment i should connect pins differently - cpu_a[2] to my a0 memory pins. is it right? something is not right, since with this i will miss one address line from the top - msb on my cpu is cpu_a[22] and now it is connected to the a21 pin of my flash memory chip... --- Quote End ---
Ooh! I use DYNAMIC alignment for memory, not native - I messed up alignment types.
So I guess I am good in this part of the issue
http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif My CPU_A[1] goes correctly to A0 of memory chips
http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/laugh.gif
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