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Altera_Forum's avatar
Altera_Forum
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16 years ago

problems with debug Nios

I have created the project in SOPC Nios + onchip_ram + jtag_uart + two pio_led + external IRQ + timer + pll + C code. This project with Nios works, all OK. Debug in the IDE works too. After that I in the top project with Nios have added the external module. External module consisting of several hdl files. The external module is not connected with Nios.

After that problems have appeared problems with Debug in the IDE.

in console is message

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Pausing target processor: not responding.

Resetting and trying again: OK

Initializing CPU cache (if present)

OK

Downloading 00020000 ( 0%)assertion "m_state == STATE_DEBUG" failed: file "nios2

debug.cpp", line 1757

C:\altera\80\nios2eds\bin\nios2-download: line 594: 1220 Hangup

nios2-gdb-server --cable 'USB-Blaster [USB-0]' --instance 0 --tcpport none --w

rite-pid ./Debug/nios2-download.pid ./Debug/nios_test_led.elf.srec

Sometimes in console is message

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Processor is already paused

Initializing CPU cache (if present)

OK

Downloading 00020000 ( 0%)

Downloaded 16KB in 0.8s (20.0KB/s)

Verifying 00020000 ( 0%)

Verify failed between address 0x20000 and 0x23CFF

Leaving target processor paused

Sometimes in console is message

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Pausing target processor: not responding.

Resetting and trying again: FAILED

Leaving target processor paused

I use Q8.0 sp1. Where there can be a mistake?

Thank

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    It's hard to say anything. You need to provide more information.

    For example:

    - is the external module a sopc module? Or maybe is it a component included in your Quartus top level and simply connected to sopc block?

    - how has the connection to Nios been made?

    - does your design meets timing constraints?

    Regards

    Cris
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    external module it's my user logic, I have written it without sopc.

    Nios has not connection with external module.

    my design hasnot special timing constraints.

    Regards

    serg
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    the state debug message appeared a long time ago with usb blaster rev b. when we had jtag issues.

    we had replaced the flat yellow cable with a short (<10cm) ribbon cable and rechecked that the jtag implmented on our custom boards as mentioned in the device handbooks.

    could it be that the new added logic just produced more noise and disturbs the jtag ?

    with added logic the jtag fails without it works ?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    with added logic the jtag fails without it works ?

    --- Quote End ---

    without added logic jtag is works. line Jtag cable = 15 cm.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    my design hasnot special timing constraints.

    --- Quote End ---

    Almost every design has timing constraints. You must constrain your design to be sure that it can run at the frequency you use.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    Almost every design has timing constraints. You must constrain your design to be sure that it can run at the frequency you use.

    --- Quote End ---

    I agree with you, that almost every design has timing constraints. After compilation I have checked that actual frequency = 205MHz and she higher than required frequency = 100MHz. Here all OK.

    Quartus has any special timing constraints for debug uart?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You should check the hold requirements too. Do you use Timequest or the classical timing analyser?

    The timing settings for the debug uart are setup automatically, as long as you give the system clock frequency.

    Do you have all the licenses or are you in Opencore evaluation mode? In the latter case, be careful not to close the small Opencore alert box, it would make the licensed part stop.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    could it be that the new added logic just produced more noise and disturbs the jtag ?

    with added logic the jtag fails without it works ?

    --- Quote End ---

    I have solved the problem. MSchmitt, You are right. After the analysis of jtag signals on pcb, I found a signal which influences on TCK. After I have disconnected him from altera, debug jtag for nios began to work.

    Thanks all for the help.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    your welcome..

    is good to know that that little help, helped to solve the problem or even a workaround.