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Altera_Forum's avatar
Altera_Forum
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15 years ago

problems with debug Nios

I have created the project in SOPC Nios + onchip_ram + jtag_uart + two pio_led + external IRQ + timer + pll + C code. This project with Nios works, all OK. Debug in the IDE works too. After that I in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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could it be that the new added logic just produced more noise and disturbs the jtag ?

with added logic the jtag fails without it works ?

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I have solved the problem. MSchmitt, You are right. After the analysis of jtag signals on pcb, I found a signal which influences on TCK. After I have disconnected him from altera, debug jtag for nios began to work.

Thanks all for the help.