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Altera_Forum's avatar
Altera_Forum
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15 years ago

problems with debug Nios

I have created the project in SOPC Nios + onchip_ram + jtag_uart + two pio_led + external IRQ + timer + pll + C code. This project with Nios works, all OK. Debug in the IDE works too. After that I in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Almost every design has timing constraints. You must constrain your design to be sure that it can run at the frequency you use.

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I agree with you, that almost every design has timing constraints. After compilation I have checked that actual frequency = 205MHz and she higher than required frequency = 100MHz. Here all OK.

Quartus has any special timing constraints for debug uart?