Problem with SDRAM on DE2 board

I am using the Altera DE2 board (Cyclone II FPGA), Quartus 8.0 and Nios II IDE 8.0. I am having trouble using SDRAM in my design. Following are the details:

1. I have included a PLL component in my design. Phase shift is -54 deg (-3 ns) and the output of the PLL is connected to the SDRAM clk.

2. I have set the reset vector and exception vector of my Nios II processor to be in the SDRAM (within the SOPC builder).

3. While building the system library for my application (inside the Nios II IDE) I specify the heap, stack, text memory to be SDRAM.

There is no compilation error within Quartus II or build error inside Nios II IDE. compilation and build are successful. But when I try to run the application, there is no output. The Nios II output terminal opens, and the console remains blank. When I change the settings mentioned in points 2 and 3 above to 'SRAM' the application works perfectly and prints the output to the console.

I kept the above settings as 'SRAM' and tried to "test" the SDRAM by reading to and writing from it (Reference: 'Rapid Prototyping of Digital Systems' by Hamblen). The "test" was positive. Returned no errors.

Is there any other setting for the SDRAM that I am missing?

I would appreciate any help/insights.

Thanks!