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Altera_Forum
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16 years ago

Problem with SDRAM on DE2 board

I am using the Altera DE2 board (Cyclone II FPGA), Quartus 8.0 and Nios II IDE 8.0. I am having trouble using SDRAM in my design. Following are the details: 1. I have included a PLL component ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I am using the same configuration (DE2 Cyclone 2) and I have the same problem with the SDRAM.

(the program does'nt launch after downloading: Starting processor at address ... then NIOS console remains blank )

I'm just trying to run an helloworld exampe program from SDRAM.

Reset vector and exception vector of nios are in SDRAM.

Linker setting: .bss .heap .rodata .rwdata .stack .txt => SDRAM

i tried different tuning of the pll but it does'nt change anything.

If someone have any ideas, I would be happy to try !