Not able to interface SDRAM with nios Processor

Question

I have made a system with Nios processor, JTAG-UART, SDRAM(8MB), Clock Signal IP core, on chip memory. I am not able to implement the hello World Program. The nios console doesnt show anything except for :

USB-Blaster on localhost[USB-0] device ID:1 instance ID-0 name JTAG-UART_0

The problem is with the SDRAM because the system working fine without it and printing hello World. Earlier posts suggest checking the clock skew but I havent used the PLL. The clock signal IP core( clock signals for DE-series board Pheripherals) is supposed to take of the skew on its own. Any suggestion on what could be wrong ?

altera_forum · Answer

What dev board are you using? It should have come with an example that uses SDRAM. Use that as your starting point.

If that doesn't work, load a pre-built .sof file that uses SDRAM to verify that your hardware is working.

altera_forum · Answer

Gal is right... what board are you using actually?

altera_forum · Answer

I am using the DE2 board. I tried to follow the step given in their example but their example is using a PLL.

altera_forum · Answer

The design example uses a PLL for good reason. The clock out to the SDRAM will need to be phase shifted with respect to the clock driving the logic.

--- Quote Start ---

The clock signal IP core( clock signals for DE-series board Pheripherals) is supposed to take of the skew on its own

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I'm not sure what you mean by this. What 'IP core' is it referring to if it's not a PLL?

Cheers,

Alex

altera_forum · Answer

There is a clock signals IP core in the University Programs Module that I am using.

This is what the description says in the tutorial document:

"The clock skew depends on physical characteristics of the DE2 board. For proper operation of the SDRAM chip,it is necessary that its clock signal, DRAM_CLK, leads the Nios II system clock, CLOCK_50, by 3 nanoseconds.This can be accomplished by using a phase-locked loop (PLL) circuit which can be manually created using the MegaWizard plug-in. It can also be created automatically using the Clock Signals IP core provided by the Altera University Program "

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Not able to interface SDRAM with nios Processor

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