Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Not able to interface SDRAM with nios Processor

I have made a system with Nios processor, JTAG-UART, SDRAM(8MB), Clock Signal IP core, on chip memory. I am not able to implement the hello World Program. The nios console doesnt show anything except...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

The "Clock Signals IP core" is a wrapper, which instantiates a PLL with settings specific to the hardware you're using. So, you are using a PLL it's just hidden behind this IP core.

All I can suggest is that you revisit all the settings you are presented with in configuring that IP core. Alternatively, you could try instantiating the PLL directly. This will require more settings. However, you will be able to take these from the reference design available for the dev board.

Cheers,

Alex