Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorNot able to interface SDRAM with nios Processor
I have made a system with Nios processor, JTAG-UART, SDRAM(8MB), Clock Signal IP core, on chip memory. I am not able to implement the hello World Program. The nios console doesnt show anything except...
Altera_ForumHonored Contributor
Honored ContributorThe design example uses a PLL for good reason. The clock out to the SDRAM will need to be phase shifted with respect to the clock driving the logic.
--- Quote Start --- The clock signal IP core( clock signals for DE-series board Pheripherals) is supposed to take of the skew on its own --- Quote End --- I'm not sure what you mean by this. What 'IP core' is it referring to if it's not a PLL? Cheers, Alex
