Not able to interface SDRAM with nios Processor

There is a clock signals IP core in the University Programs Module that I am using.

This is what the description says in the tutorial document:

"The clock skew depends on physical characteristics of the DE2 board. For proper operation of the SDRAM chip,it is necessary that its clock signal, DRAM_CLK, leads the Nios II system clock, CLOCK_50, by 3 nanoseconds.This can be accomplished by using a phase-locked loop (PLL) circuit which can be manually created using the MegaWizard plug-in. It can also be created automatically using the Clock Signals IP core provided by the Altera University Program "