NIOS power up and reset

The most I've ever done is create a counter that counts up to some value and stops. The counter starts at 0, and the external reset pin will reset the counter to 0. All other circuits on the Altera chip use a registered version of the counter's count enable signal for their reset.

This has the effect of holding the chip in reset for a certain amount of time after either the external reset is released, or the chip switches from configuration mode to user mode.

The example designs for the various Altera Nios demo boards have a delayed-reset counter that does about the same thing; you could look at it.

How long do you need to hold reset? I'm not sure; I usually aim for a few microseconds, but you may want longer if you need a PLL to stabilize, for example.

I have a power supply monitor IC that holds reset active (low) for 200 msec after the power supplies are stabilized.

But If I power up and the fpga configures and the software starts running, and then cause the reset to go low and release it, the fpga stays configured but the software never starts running.

Anyone got any input on this.

Thanks

George

Well if you mean how many clock cycles a nios needs to initialize after external hw-reset ... no idea. i guess that is handled inside the cios core.

But i agree with Mike that altera has a "delay_reset_block" between the fpga input pin and the nios reset input. If you have a PLL to create the nios clock and the sdram (phaseshift) then the pll needs some time after CONF_DONE to settle. during that time the clock could be unstable. The pll offers a locked output that can be used to hold the reset inside the fpga to an active state until the pll is locked and stable.

As far a i knew that delay block is used to gibe the pll the chance to locked before nios starts. But i am not shure if the pll locked output of the pll is a way to save that delay block and its counters and replace it by the shortest time possible for that pll to lock.

Regards.

Michael Schmitt

This is rather silly.

How come someone from Alter can not answer this question?

We're all just guessing.

What are the timing requirements for reset_n and config_done on a cyclone fpga??

george

George,

from what I understand, Nios II does not require any initialization clocks before releasing reset_n. Assuming your clock is stable, you can connect your reset_n pin to reset Nios.

Altera uses the reset_counter to wait until the PLL stabalizes. Personally, I use the PLL_LOCKED signal, and logically OR it with the reset_n input pin (if either is low, then reset Nios). I use an AND symbol to accomplish this. (since we are OR'ing zeros)

Hope this helps,

-Terry

George,

I (from Altera) concur with Terry on this one. The delayed reset block was something we tossed in to work around PLL locked signal behavior; it worked adequately, but a couple of gates to AND-in (for example) PLL lock with reset_n in should do fine. The down-side of this is that any glitches on the lock signal cause multiple reset pulses into the Nios system... for this reason, I feel better about having both a delay block and the gate.

For what its worth, this stuf is documented:

- PLL lock (maximum time) -- for Stratix II (other corresponding docs available in device handbook timing chapters for each Altera device family): http://www.altera.com/literature/hb/stx2/s...x2_sii51005.pdf (http://www.altera.com/literature/hb/stx2/stx2_sii51005.pdf)

- Here is similar information for conf_done: http://www.altera.com/literature/hb/stx2/s...x2_sii52007.pdf (http://www.altera.com/literature/hb/stx2/stx2_sii52007.pdf)

The latter doc is *long*, but covers everything you wanted to know about configuration (each mode documented in detail).

Again, the above is for stratix ii. For cyclone, visit the Altera literature page, go to cyclone docs, and check out the corresponding device handbook chapters (each a separate PDF).