NIOS power up and reset

Well if you mean how many clock cycles a nios needs to initialize after external hw-reset ... no idea. i guess that is handled inside the cios core.

But i agree with Mike that altera has a "delay_reset_block" between the fpga input pin and the nios reset input. If you have a PLL to create the nios clock and the sdram (phaseshift) then the pll needs some time after CONF_DONE to settle. during that time the clock could be unstable. The pll offers a locked output that can be used to hold the reset inside the fpga to an active state until the pll is locked and stable.

As far a i knew that delay block is used to gibe the pll the chance to locked before nios starts. But i am not shure if the pll locked output of the pll is a way to save that delay block and its counters and replace it by the shortest time possible for that pll to lock.

Regards.

Michael Schmitt