NIOS power up and reset

George,

I (from Altera) concur with Terry on this one. The delayed reset block was something we tossed in to work around PLL locked signal behavior; it worked adequately, but a couple of gates to AND-in (for example) PLL lock with reset_n in should do fine. The down-side of this is that any glitches on the lock signal cause multiple reset pulses into the Nios system... for this reason, I feel better about having both a delay block and the gate.

For what its worth, this stuf is documented:

- PLL lock (maximum time) -- for Stratix II (other corresponding docs available in device handbook timing chapters for each Altera device family): http://www.altera.com/literature/hb/stx2/s...x2_sii51005.pdf (http://www.altera.com/literature/hb/stx2/stx2_sii51005.pdf)

- Here is similar information for conf_done: http://www.altera.com/literature/hb/stx2/s...x2_sii52007.pdf (http://www.altera.com/literature/hb/stx2/stx2_sii52007.pdf)

The latter doc is *long*, but covers everything you wanted to know about configuration (each mode documented in detail).

Again, the above is for stratix ii. For cyclone, visit the Altera literature page, go to cyclone docs, and check out the corresponding device handbook chapters (each a separate PDF).