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Altera_Forum's avatar
Altera_Forum
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16 years ago

Nios not responds, then FAILs, then pauses

intro: I am trying to instantiate a Nios II system on a Stratix I FPGA. The Nios takes in as input a clk and a reset signal, and outputs various signals through PIO. I am using on-chip memory to store my code for the Nios, because I don't have access to external memory. I also have a sys_clk_timer and sysid in my SOPC configuration.

problem: When I try to run my software program (or the Hello World! program) I get the following message: 


Using cable "USB-Blaster ", device 1, instance 0x00
Pausing target processor: not responding.
Resetting and trying again: FAILED
Leaving target processor paused

Anybody know what can cause this. My design worked prior to using a Nios (the Nios will make my development much easier), so I am assuming my pin assignments are correct. Does the reset to the Nios have to be a certain way. Currently I have a counter that waits until 0xC, bring reset high, then waits until 0xF, and brings reset low. I did this just in case the Nios needs to be reset.

Please give me suggestions! All I need my Nios to do is to communicate with the User though RS-232 and send I/O back to my HDL design.

Thanks!

-Ben

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    rest for SOPC Builder is reset_n and is active low. your reset is inverted.

    --dalon
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Changing the reset to active low fixed that problem (I feel stupid for missing that) ... but now I have the famous "Verify failed between address ..." message, shown below. I read through the forum but didn't see anything that was obvious. Any suggestions? What would cause on chip memory to fail verification. I had this problem on another board when using external memory, but that turned out to be timing to the chip. This memory is in the FPGA, so I don't know what could go wrong. I am using the M4K memory on a Stratix I.

    Thanks,

    -Ben 

    
Using cable "USB-Blaster ", device 1, instance 0x00
Pausing target processor: OK
Reading System ID at address 0x000410A8: verified
Initializing CPU cache (if present)
OK
Downloading 00020000 ( 0%)
Downloaded 56KB in 0.9s (62.2KB/s)
Verifying 00020000 ( 0%)
Verify failed between address 0x20000 and 0x2DEBF
Leaving target processor paused
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Is you on-chip memory indeed at address 0x20000 ? Do you have any component with an avalon master that could overwrite that memory by mistake?

    Does your Quartus project meet timing requirements? You need to look for critical warnings from Timequest.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I resolved my issue!

    Instead of instantiating my CPLL in my HDL logic, I instantiated it inside SOPC Builder. Then, my processor woke up in the Nios IDE.

    Then, I was told

    --- Quote Start ---

    Adding PLL inside SOPC builder can let SOPC builder to generate right reset logic automatically. Instancing PLL outside SOPC, doesn't contain power on reset logic for the system. You may need to design a power on reset logic outside SOPC to drive SOPC system's reset input.

    --- Quote End ---

    .

    So the lessons I have learned so far this week are:

    1. reset_n is active low

    2. always instantiate CPLL inside SOPC Builder because computers are smarter than people
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I would still verify that your timing constraints for the design are correct. This cannot be ignored.

    Jake