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Altera_Forum
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16 years ago

Nios not responds, then FAILs, then pauses

intro: I am trying to instantiate a Nios II system on a Stratix I FPGA. The Nios takes in as input a clk and a reset signal, and outputs various signals through PIO. I am using on-chip memory to s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Changing the reset to active low fixed that problem (I feel stupid for missing that) ... but now I have the famous "Verify failed between address ..." message, shown below. I read through the forum but didn't see anything that was obvious. Any suggestions? What would cause on chip memory to fail verification. I had this problem on another board when using external memory, but that turned out to be timing to the chip. This memory is in the FPGA, so I don't know what could go wrong. I am using the M4K memory on a Stratix I.

Thanks,

-Ben 


Using cable "USB-Blaster ", device 1, instance 0x00
Pausing target processor: OK
Reading System ID at address 0x000410A8: verified
Initializing CPU cache (if present)
OK
Downloading 00020000 ( 0%)
Downloaded 56KB in 0.9s (62.2KB/s)
Verifying 00020000 ( 0%)
Verify failed between address 0x20000 and 0x2DEBF
Leaving target processor paused