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Altera_Forum
Honored Contributor
Honored ContributorNios not responds, then FAILs, then pauses
intro: I am trying to instantiate a Nios II system on a Stratix I FPGA. The Nios takes in as input a clk and a reset signal, and outputs various signals through PIO. I am using on-chip memory to s...
Altera_ForumHonored Contributor
Honored ContributorI would still verify that your timing constraints for the design are correct. This cannot be ignored.
Jake
