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Honored Contributor
Honored ContributorNios not responds, then FAILs, then pauses
intro: I am trying to instantiate a Nios II system on a Stratix I FPGA. The Nios takes in as input a clk and a reset signal, and outputs various signals through PIO. I am using on-chip memory to s...
Altera_ForumHonored Contributor
Honored ContributorI resolved my issue!
Instead of instantiating my CPLL in my HDL logic, I instantiated it inside SOPC Builder. Then, my processor woke up in the Nios IDE. Then, I was told --- Quote Start --- Adding PLL inside SOPC builder can let SOPC builder to generate right reset logic automatically. Instancing PLL outside SOPC, doesn't contain power on reset logic for the system. You may need to design a power on reset logic outside SOPC to drive SOPC system's reset input. --- Quote End --- . So the lessons I have learned so far this week are: 1. reset_n is active low 2. always instantiate CPLL inside SOPC Builder because computers are smarter than people
