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Altera_Forum's avatar
Altera_Forum
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13 years ago

NIOS II Eclipse can't read ID and TimeStamp

When setting up the Run Configuration, under Target Connection, I can see the USB-Blaster but the IDE can not read the expected

ID and system Timestamp. The FPGA was programmed to 100%. Is that related to the fact that I am using a timelimited.sof ?

When I try using System Console to setup a path to a master it does find it and maps it as nios2_0 but I can't do a master_read_32 it tells me that it is

running, so

When I try using System Console to do any processor_stop or processor_reset I get a message that "...the target is broken and needs to be reset":cry:

What other low level means are there to debug this issue?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    If you are using a time limited .sof, you should have a window opening just after you configured the FPGA, saying that you are running in Opencore evaluation mode. Do you close that window? If you do then the CPU stops working. You need to keep that window open when you use the IDE.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    If you are using a time limited .sof, you should have a window opening just after you configured the FPGA, saying that you are running in Opencore evaluation mode. Do you close that window? If you do then the CPU stops working. You need to keep that window open when you use the IDE.

    --- Quote End ---

    Thanks for helping me. I did what you said but I still get the same results even after refreshing many times. I read another case that had the same problem:

    http://www.alteraforum.com/forum/showthread.php?t=37386

    What is puzzling me is why Altera put the option of skipping the ID and TimeStamp verification and why the refresh? is it because it is a common problem?

    I am really stuck now:(
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    can you use signaltap and check the clock and reset signals to the CPU? A very common mistake is to use the wrong polarity on the reset signal. Usually a QSys/SOPC builder reset input is active low (when it is called reset_n) while most IPs use a active high reset.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I have faced to this problem (can't read ID and timestamp although "system-console" can). to workaround, i close and restart the nios eclipse.

    Obviously, It can also occurs when the Hardware (.sof) (precisely the Qsys generated) doesn't match the BSP (in Nios Eclipse project)