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Altera_Forum
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13 years ago

NIOS II Eclipse can't read ID and TimeStamp

When setting up the Run Configuration, under Target Connection, I can see the USB-Blaster but the IDE can not read the expected ID and system Timestamp. The FPGA was programmed to 100%. Is that re...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

can you use signaltap and check the clock and reset signals to the CPU? A very common mistake is to use the wrong polarity on the reset signal. Usually a QSys/SOPC builder reset input is active low (when it is called reset_n) while most IPs use a active high reset.