Multiple Clock

Hi!

I think you can try to get the other clocks from a fast clock by using PLL.

The clock generation is not the problem.

The clock-domain crossing logic that is created by the SOPC builder can not be synthesised or simulated.

Add SignalTap II to the list as well.

I used a seperate clock for a custom peripheral on a uKit board, it built and works fine. The periperhal clock was 1/3 slower than system. Both clocks originated from same PLL.

Have you tried a faster clock for CPU and slower for other, just as a test?

I found the problem during the sythesis. SOPC Builder creates for the clock domain crossing logic:

endofpacket_bus_pipe : dma_0_control_port_slave_X_cpu_data_master_bus_pipe

port map(

data_out (31 DOWNTO 1) => open,

data_out (0 downto 0) => internal_slave_endofpacket,

clk1 => slave_clk,

clk2 => master_clk,

data_in => std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(master_endofpacket)),

reset_clk1_n => slave_reset_n,

reset_clk2_n => master_reset_n

);

Quartus doen't like this line : data_out (0 downto 0) => internal_slave_endofpacket,

after changing to data_out (0) => internal_slave_endofpacket,

synthesis works without a problem, but modelsim show some other problems http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif

@joelw: no I didn&#39;t try. But I will do.

Hi there,

I had the same problem. Make sure you are running the service pack for 4.2. This fixes things.

Good Luck.

hi sja,

thx for the hint. Now synthesis runs without a problem. Did you try to simulate your design with Modelsim?

There I get still errors.

Hi there revolt,

Sorry. I didn&#39;t go down the Modelsim path so I can&#39;t offer any suggestions there.

I hope you work it out.

Good luck

sja