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Honored Contributor
Honored ContributorMultiple Clock
Hi everyone, I try to implement a system with multiple clock domains. The NIOS system run with 50 Mhz and some avalon components should run with 100 Mhz (DMA, FIFO, internal SRAM). SOPC Builder...
Altera_ForumHonored Contributor
Honored ContributorI found the problem during the sythesis. SOPC Builder creates for the clock domain crossing logic:
endofpacket_bus_pipe : dma_0_control_port_slave_X_cpu_data_master_bus_pipe port map( data_out (31 DOWNTO 1) => open, data_out (0 downto 0) => internal_slave_endofpacket, clk1 => slave_clk, clk2 => master_clk, data_in => std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(master_endofpacket)), reset_clk1_n => slave_reset_n, reset_clk2_n => master_reset_n ); Quartus doen't like this line : data_out (0 downto 0) => internal_slave_endofpacket, after changing to data_out (0) => internal_slave_endofpacket, synthesis works without a problem, but modelsim show some other problems http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif @joelw: no I didn't try. But I will do.
