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Altera_Forum
Honored Contributor
Honored ContributorMultiple Clock
Hi everyone, I try to implement a system with multiple clock domains. The NIOS system run with 50 Mhz and some avalon components should run with 100 Mhz (DMA, FIFO, internal SRAM). SOPC Builder...
Altera_ForumHonored Contributor
Honored Contributorhi sja,
thx for the hint. Now synthesis runs without a problem. Did you try to simulate your design with Modelsim? There I get still errors.
