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Altera_Forum
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21 years ago

Multiple-Clock Domain with 2 Nios?

Hello,

I tried the new multiple-clock domain feature (Quartus 4.2, Nios1.1) with a Cyclone evaluation board.

One Nios should boot from flash and run out of SDRAM, the other Nios should also boot out of the flash but run out of SRAM.

The common components are the tri-state-bridge and the SRAM/flash behind, from where both Nios are booting.

With one single clock the design seems to work.

After adding a second clock (multiple-clock domain) with a different clock rate (50 MHz and 75 MHz) I run into problems.

First of all Quartus complains that it can't connect a std_logic_vector(with 0 downto 0) to a std_logic signal in all generated design files that have to do with the clock crossing.

(Error: VHDL error at ext_tri_state_bridge_avalon_slave_X_nios2_data_master.vhd(1014): type of identifier "internal_slave_endofpacket" does not agree with its usage as std_logic_vector type)

After editing the lines from

data_out (0 DOWNTO 0) => internal_slave_endofpacket

to

data_out (0) => internal_slave_endofpacket

Quartus was happy and compiling the whole stuff.

After programming the flash on the evalboard via Flash-Programmer and resetting the board ... nothing happened.

I connected the leds to the Nios to let them blinking via software, but nothing happened.

I also can't attach the Debugger (via IDE).

When downloading the software directly via Debugger it is working, the LEDs are blinking.

So it looks like a booting problem from flash, but I am not sure !?!??!

Has anybody some ideas where to look?

Thanks,

damc

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    Hi BadOmen,

    In the first one, Nios, SDRAM controller, timer, uart, some PIOs, some interface to user logic and access to the tri-state-bridge (for booting).

    In the second, Nios, uart, tri-state-bridge (with SRAM, Flash), some PIOs and also some interface to user logic.

    The only common interface is the tri-state-bridge (instruction and data).

    Why do you ask?
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    I haven't seen those error message before, but re-reading your original post has made me curious. You say that both processors boot out of Flash. That would mean that each needs a bootloader (I don't think you will get two of them). Can you copy and paste the text from the flash programmer into the post. I'll take a look and see what's going on.

    Back to that error message. Do you have a signal in your system that is usually a bus, but has been minimized to a single line? I have never tried to declare a std_logic_vector (0 downto 0) before but I thought that would be a perfectly valid statement (valid, but not clean coding). If I don&#39;t get back to you right away send another message since I happen to be working with the clock crossing features right now (before the weekend roles around and I start forgetting things http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif ).
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    Yes, why shouldn&#39; it possible that both Nios boot out of the same flash?

    The reset address of the first one is flash+0 and the second one gets flash+0x100000.

    Here is the text of the flash programmer for the first nios system:

    # ! /bin/sh# # This file was automatically generated by the Nios II IDE Flash Programmer.# # It will be overwritten when the flash programmer options change.#

    cd D:/temp/EvalBoard_Cyclone/MP3_Player/software/MP3_Player_eth_ide/Debug

    # Creating .flash file for the FPGA configuration

    $SOPC_KIT_NIOS2/bin/sof2flash --flash=U5 --offset=0x600000 --input=D:/temp/

    EvalBoard_Cyclone/MP3_Player/MP3_Player.sof --output=MP3_Player.

    flash

    Info: *******************************************************************

    Info: Running Quartus II Convert_programming_file

    Info: Command: quartus_cpf --no_banner --convert D:/temp/Ev

    alBoard_Cyclone/MP3_Player/MP3_Player.sof MP3_Player.rbf

    Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings

    Info: Processing ended: Thu Jan 27 09:41:31 2005

    Info: Elapsed time: 00:00:01

    # Programming flash with the FPGA configuration

    $SOPC_KIT_NIOS2/bin/nios2-flash-programmer --input=MP3_Player.flash --sof=$SOPC_

    KIT_NIOS2/components/altera_nios_dev_board_cyclone_1c20/system/altera_nios_dev_b

    oard_cyclone_1c20.sof --cable=&#39;USB-Blaster [USB-0]&#39; --base=0x00800000

    27.01.2005 09:41:35 - (INFO) nios2-flash-programmer: Launching Quartus Programme

    r to download:

    D:/Altera/niosii_v11_build137d/components/altera_nios_dev_board_cyclone_1c2

    0/system/altera_nios_dev_board_cyclone_1c20.sof

    Pre-Reading 434KBytes of data from U5:

    |----.----+----.----|

    ********************* (4.176 sec).

    Erasing 7 Sectors:

    |----.----+----.----|

    ********************* (4.607 sec).

    Writing 448KBytes :

    |----.----+----.----|

    ********************* (22.242 sec).

    Verifying 448KBytes of data:

    |----.----+----.----|

    ********************* (3.705 sec).

    27.01.2005 09:42:18 - (INFO) nios2-flash-programmer: Success. Verified 448Kbytes

    written to U5.

    27.01.2005 09:42:18 - (INFO) nios2-flash-programmer: Flash programming complete

    # Creating .flash file for the project

    $SOPC_KIT_NIOS2/bin/elf2flash --flash=U5 --base=0x01000000 --end=0x1800000 --res

    et=0x1000000 --input=MP3_Player_eth_ide.elf --output=ext_flash.flash --boot=$SOP

    C_KIT_NIOS2/components/altera_nios2/boot_loader_cfi.srec

    # Programming flash with the project

    $SOPC_KIT_NIOS2/bin/nios2-flash-programmer --input=ext_flash.flash --sof=__NO_SO

    F_PLEASE__ --cable=&#39;USB-Blaster [USB-0]&#39; --base=0x00800000

    27.01.2005 09:42:20 - (INFO) nios2-flash-programmer: SOF-download skipped.

    Pre-Reading 163KBytes of data from U5:

    |----.----+----.----|

    ********************* (1.853 sec).

    Erasing 3 Sectors:

    |----.----+----.----|

    ********************* (2.093 sec).

    Writing 192KBytes :

    |----.----+----.----|

    ********************* (9.643 sec).

    Verifying 192KBytes of data:

    |----.----+----.----|

    ********************* (1.603 sec).

    27.01.2005 09:42:38 - (INFO) nios2-flash-programmer: Success. Verified 192Kbytes

    written to U5.

    27.01.2005 09:42:38 - (INFO) nios2-flash-programmer: Flash programming complete

    The error message came from Quartus and the source is a file generated by the SOPC-Builder itself, it has nothing to do with my own written code.

    If you want I can send you a very small Quartus project (SOPC-builder design with 2 PIOs and 1 user interface) that shows the error message.
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    When you program the flash twice (once per application), I&#39;m guessing you&#39;ll see the last one programmed work and the first one will not.

    That caption shows me that your hardware is programmed, and the software "MP3_Player_eth_ide.elf" has been placed into flash. My next question is: between these two CPUs, is there any interaction or do they basically live in their own little world?

    I have a few ideas for you, but depending on your setup one is better than the other.
  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    If I have a multi processor system, I MUST have two projects in the IDE and I expect that the flash-programmer is so intelligent that it erases only the necessary parts of the flash.... if not, probably I can use the "Program a file into flash" feature to store the software for the second Nios.

    But until now I just tried to get the first Nios project to run.... and failed.

    The only interaction between the both CPUs is the flash during booting and a fifo in-between for data transfers from one to the other.

    What I started today is porting the design to a StratixII eval board, there I can run the whole design with 75 MHz and must not care about the multi clock feature. Sure this will not solve the booting issue (if it is one)...