Occasional ContributormSGDMA MM to MM : issue reading from Avalon UART FIFO
Hi,
On a DE0 Nano Soc I am trying to setup a DMA from a FIFOed Avalon UART IP, to the DDR3 memory of the HPS, under control of a NIOS processor.
The UART is a Memory-mapped Avalon Slave, and the data it receives is available by reading one specific base address. The UART has an embedded FIFO, so each read operation to this address returns the next value in the FIFO.
When I read the UART FIFO address "manually" from the NIOS program, no problem, I retrieve the characters successfully.
Then I tried to build an extended DMA descriptor instructing the mSGDMA to perform a transfer with the UART FIFO address as the source address, some address in DDR as the destination address, and with a read stride of 0, such that consecutive reads that the DMA performs are always at the same address (i.e. the UART FIFO reading address, effectively emptying the FIFO as it goes).
Somehow this fails to read the UART FIFO data, after the DMA I check the UART FIFO level and it is still the same.
My code boils down to this:
alt_msgdma_construct_extended_mm_to_mm_descriptor(
MSGDMADev,
&MSGDMA_DESC_EXT,
(void*)FIFOED_AVALON_UART_2_BASE, /* read address */
(void*)BUF,
frameLength , /* size in bytes of data*/
0, /*control*/
0, /* sequence_number */
0, /* read_burst_count */
0, /* write_burst_count */
0, /*read_stride*/
1 /*write_stride*/
);
alt_msgdma_extended_descriptor_sync_transfer(MSGDMADev, &MSGDMA_DESC_EXT);
What am I doing wrong ? It is not shown above but of course I check the return codes from these two calls and they are OK.
What is a good way to investigate what the mSGDMA actually does and why it fails ?)
Thanks
