mSGDMA MM to MM : issue reading from Avalon UART FIFO

Hi,

I checked the video, but this is an example of Avalon-ST to Avalon-MM transfer.

In my case I need an Avalon-MM to Avalon-MM transfer.

I first tested it with a transfer from OnChip memory to DDR, with the default stride of 1 word increment at each transfer, and it works fine (and yes I have Linux running on the HPS side and initializing the DDR)

It is only when I changed the source in the descriptor to the base address of the UART IP, and adjust the read stride to 0 (so that successive transfers always read the same input adress), that things apparently don't work anymore, somehow the read transactions on the Avalon bus are not performed because the UART FIFO level does not change after the DMA operation.

About the prefetcher: no I have not yet used this option. Can you please explain how it could be relevant to my problem ? I see it as a performance optmisation option only?

Regards,

Julien