Forum Discussion
Julien
Occasional Contributor
7 years agomSGDMA MM to MM : issue reading from Avalon UART FIFO
Hi, On a DE0 Nano Soc I am trying to setup a DMA from a FIFOed Avalon UART IP, to the DDR3 memory of the HPS, under control of a NIOS processor. The UART is a Memory-mapped Avalon Slave, and the da...
anilinintel
Occasional Contributor
7 years agofrom this conversation. can someone help me in writing a c code for msgdma prefetcher enabled. with great difficulty i am able to do MM-to-MM transfers from ddr4 to custom memory block via mSGDMA IP block. but now i want to do with prefetcher enabled in it which i think it will save more cycles. plz i dont want videos/reference HAL driver pdf's. i had a look on all those. Thanks