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Julien's avatar
Julien
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

mSGDMA MM to MM : issue reading from Avalon UART FIFO

Hi, On a DE0 Nano Soc I am trying to setup a DMA from a FIFOed Avalon UART IP, to the DDR3 memory of the HPS, under control of a NIOS processor. The UART is a Memory-mapped Avalon Slave, and the da...
FawazJ_Altera's avatar
FawazJ_Altera
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hello,

The concept should be the same, we have used ST to MM in the video since the source of the pattern generator was ST, and to simplify the design we used ST to MM.

Prefetcher mode enables the external descriptor master connection.This means the descriptors location will be outside the mSGDMA. With the prefetcher enabled, it will complicate the mSGDMA flow.

Are you using the UART RS-232 Serial Port intel FPGA IP ?

once I know from you which UART IP, I will do a quick test.

Thanks