Forum Discussion
Julien
Occasional Contributor
Occasional ContributormSGDMA MM to MM : issue reading from Avalon UART FIFO
Hi, On a DE0 Nano Soc I am trying to setup a DMA from a FIFOed Avalon UART IP, to the DDR3 memory of the HPS, under control of a NIOS processor. The UART is a Memory-mapped Avalon Slave, and the da...
JulienOccasional Contributor
Occasional ContributorI am using the "FIFOed Avalon UART IP" from here:
https://fpgawiki.intel.com/wiki/FIFOed_Avalon_Uart
( I am using the latest version)
When I read the UART FIFO using NIOS code (i.e. using IORD_FIFOED_AVALON_UART_RXDATA macro that wraps an "ldwio" NIOS instruction to access the FIFO base address to pop the FIFO), it works fine. I assumed that it would be fine for the mSGDMA to be doing the read access at this FIFO base address, but there must be something different between what the ldwio instruction does and what the DMA read access does.
