mSGDMA MM to MM : issue reading from Avalon UART FIFO

I am using the "FIFOed Avalon UART IP" from here:

https://fpgawiki.intel.com/wiki/FIFOed_Avalon_Uart

( I am using the latest version)

When I read the UART FIFO using NIOS code (i.e. using IORD_FIFOED_AVALON_UART_RXDATA macro that wraps an "ldwio" NIOS instruction to access the FIFO base address to pop the FIFO), it works fine. I assumed that it would be fine for the mSGDMA to be doing the read access at this FIFO base address, but there must be something different between what the ldwio instruction does and what the DMA read access does.