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Julien's avatar
Julien
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

mSGDMA MM to MM : issue reading from Avalon UART FIFO

Hi, On a DE0 Nano Soc I am trying to setup a DMA from a FIFOed Avalon UART IP, to the DDR3 memory of the HPS, under control of a NIOS processor. The UART is a Memory-mapped Avalon Slave, and the da...
FawazJ_Altera's avatar
FawazJ_Altera
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hello Julien,

Thanks for contacting Intel PSG Forum.

Have you seen this video?

https://www.youtube.com/watch?v=iaRkjkpMBH8

I gave a description on how to run mSGFMA and stream data from a source to a memory.

I did the mSGDMA to HPS DDR before. The first step I confirmed is, the data flow is correct (from source to on chip memory). Then, I changed the destination to HPS DDR. Please note that you would not be able to access HPS DDR until Linux is booting.

have you used the prefetcher mode?

Thanks